module slave_interface (

    input wire clk,
    input wire rst,


    // output signals
    output wire [31:0] o_slave_data,
    output wire        o_slave_en,
    input  wire        i_slave_busy,

    // signals between master and slave
    input  wire        i_slave_valid,
    input  wire [31:0] i_slave_data,
    output wire        o_slave_ready
    );

    parameter STATE_BUSY = 1'b1, STATE_IDLE = 1'b0;
    reg current_state, next_state;

    // generate next state
    wire handshake = i_slave_valid & o_slave_ready;
    always @(*) begin
        case (current_state)
            STATE_BUSY: begin next_state = i_slave_busy ? STATE_BUSY : STATE_IDLE; end
            STATE_IDLE: begin next_state = handshake    ? STATE_BUSY : STATE_IDLE; end
        endcase
    end

    // state transition
    always @(posedge clk) begin
        if(rst) begin
             current_state <= STATE_IDLE; 
        end
        else begin 
            current_state <= next_state;
        end
    end

    // generate output signals
    reg [31:0] data_reg;
    always @(posedge clk) begin
        if(rst) begin
            data_reg <= 32'd0;
        end
        else if(handshake) begin
            data_reg <= i_slave_data;
        end
    end

    assign o_slave_ready = (current_state == STATE_IDLE);
    assign o_slave_en    = (current_state == STATE_BUSY);
    assign o_slave_data  = {32{o_slave_en}} & data_reg;
    

endmodule